 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| SLGSSTVF16859H/V DDR 13 to 26 Bit Registered Buffer Applications: * PC1600/2100/2700/3200 DDR memory modules * 1:2 Outputs for stacked DDR DIMMS * SSTL_2 compatible data registers Features: * Compatible with JEDEC standard SSTV16859 * Differential Clock inputs * SSTL_2 data input signaling * Supports SSTL_2 class I output specifications * Output circuitry minimizes effects of SSO and unterminated lines * LVCMOS input levels on RESET pin * 2.3V-2.7V Operation for PC1600/2100/2700 * 2.5V-2.7V Operation for PC3200 * Max Clock frequency > 210MHz Pin Configuration Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B Block Diagram CLK 48 CLK 49 RESET 51 D1 35 VREF 45 . . .. R CLK D1 16 . 32 Q1A Q1B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDQ GND D13 D12 VDD VDDQ GND D11 D10 D9 GND D8 D7 RESET GND CLK CLK VDDQ VDD VREF D6 GND D5 D4 D3 GND VDDQ VDD D2 D1 GND VDDQ To 12 other channels 64-Pin TSSOP 6.1mm body, 0.50mm pitch SLGSSTVF16859H Truth Table Inputs RESET L H H H CLK CLK D X, or X, or X, or Floating Floating Floating H L L or H L or H X Q Outputs Q L H L Q0(2) Notes: 1. H = High Signal Level L = Low Signal Level = Transition LOW-to-HIGH = Transition HIGH-to-LOW X = Don't care 2. Output level prior to indicated steady state input conditions established. Silego Technology Inc. (408) 327-8800 1 PRELIMINARY Data is subject to change. May 28, 2003 SLGSSTVF16859H/V SLGSSTVF16859V Pin Configuration (Top View) Q8A VDDQ Q9A Q10A Q11A Q12A Q13A VDDQ GND D13 D12 VDD VDDQ D11 Q7A Q6A Q5A Q4A Q3A Q2A Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 D10 D9 D8 D7 RESET GND CLK CLK VDDQ VDD VREF D6 D5 D4 SLGSSTVF16859V 56-Pin VFQFN VLLD2 8.0x8.0mm body, 0.50mm pitch * Note: Connect center die pad to GND Q7B Q6B VDDQ Q5B Q4B Q3B Q2B Q1B VDDQ D1 D2 VDD VDDQ D3 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Silego Technology Inc. (408) 327-8800 GND* 2 PRELIMINARY Data is subject to change. May 28, 2003 SLGSSTVF16859H/V General Description The 14-bit SLGSSTVF16859 is a registered buffer designed for 2.3V to 2.7V VDD operating range. Inputs are SSTL_2 levels, except for the LVCMOS RESET input. Data propagation from D to Q is controlled by the differential clock (CLK/CLK) and a control signal (RESET). The rising edge of CLK (crossing with CLK falling) is used to register the Data. RESET, an LVCMOS asynchronous signal, is intended for use at the time of power-up. RESET must be held at a logic "Low" level during power up. This ensures defined outputs before a stable CLK/CLK is supplied. The SLGSSTVF16859 supports low-power standby operation. Setting RESET pin to a logic "low" disables (CLK/ CLK) receivers, and allows floating inputs to all other receivers as well (D, VREF , CLK/CLK). Additionally, all internal registers are reset, and outputs (Q) are set "low". RESET input pin must always be driven to a valid logic state "high" or "low". SLGSSTVF16859H Pin Description: PIN NUMBER 1,17,2,19,3,20,4, 21,5,22,8,23,9,24, 10,25,11,28,12, 29,13,30,14,31, 16,32 7,15,26,34,39, 43,50,58,63 6,18,27,33,38, 47,59,64 62,61,57,56,55, 53,52,44,42,41, 40,36,35 48 49 37, 46 51 45 PIN NAME QA/B (13:1) TYPE OUTPUT Q-Outputs DESCRIPTION GND VDDQ POWER POWER Ground Output supply voltage D (13:1) CLK CLK VDD RESET VREF INPUT INPUT INPUT POWER INPUT INPUT D-Inputs Positive clock input Negative clock input Core supply voltage Reset (active low) Input reference voltage Silego Technology Inc. (408) 327-8800 3 PRELIMINARY Data is subject to change. May 28, 2003 SLGSSTVF16859H/V Absolute Maximum Ratings Storage Temperature. . . . . . . . . . . . . . . . . . . . .-65oC to +150oC Supply Voltage. . . . . . . . . . . . . . . . .. . . . . . . . .-0.5 to 3.6V Input Voltage1,2. . . . . . . . . . . . . . . . . . . . . . . . .-0.5 to VDD + 0.5 Output Voltage1,2. . . . . . . . . . . . . . . . . . . . . . -0.5 to VDDQ +0.5 Input Clamp Current. . . . . . . . . . . . . . .. . . . . .-50 mA Output Clamp Current. . . . . . . . . . . . . . . . . . +50 mA Continuous Output Current. . . . . . . . . . . . . . . +50 mA VDD, VDDQ, or GND Current/Pin. . . .. . . . . . +100 mA TSSOP (H) Package Thermal Impedance3. . . . 55oC/W VLLD2 (V) Package Thermal Impedance4. . . .22oC/W Notes: 1. The input and output negative voltage ratings may be exceded if the input and output clamp currents are within limits. 2. Limited to 3.6V Max. 3. The package thermal impedance is calculated according to JESD 51-7 4. The package thermal impedance is calculated according to JESD 51-5. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device. These ratings are stress specifications only and functional operation of the device at these or other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions: PARAMETER VDD VDDQ VDDQ VREF VREF VTT VI VIH (DC) VIH (AC) VIL (DC) VIL (AC) VIH VIL VICR VID VIX IOH IOL TA DESCRIPTION Supply Voltage Output Supply Voltage for PC1600/2100/2700 Output Supply Voltage for PC3200 Reference Voltage for PC1600/2100/2700 Reference Voltage for PC3200 Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RESET Input Low Voltage Level Common mode Input Range CLK, CLK Differential Input Voltage Cross Point Voltage of Differential Clock Pair High-Level Output Current Low-Level Output Current Operating Free-Air Temperature MIN VDDQ 2.3 2.5 1.15 1.25 VREF - 0.04 0 VREF + 0.15 VREF + 0.31 2.6 1.25 1.3 VREF TYP MAX 2.7 2.7 2.7 1.35 1.35 VREF + 0.04 VDD UNITS VREF - 0.15 VREF - 0.31 1.7 0.97 0.36 ( VDD/2) 0.2 0.7 1.53 ( VDD/2) + 0.2 -16 16 70 V mA oC 0 Silego Technology Inc. (408) 327-8800 4 PRELIMINARY Data is subject to change. May 28, 2003 SLGSSTVF16859H/V SLGSSTVF16859H/V DC Electrical Characteristics - ( For PC1600/2100/2700) TA = 0 - 70oC; VDD = 2.5 +/-0.2V, VDDQ = 2.5 +/-0.2V; (unless otherwise stated) SMBL VIK VOH VOL II IDD All Inputs PARAMETERS CONDITIONS II = -18mA IOH = -100A IOH = -8mA IOL = 100A IOL = 8mA VI = VDD or GND Standby (Static) RESET = GND Operating (Static) VI = VIH(AC) or VIL(AC), RESET = VDD Dynamic operating (clock only) IDDD Dynamic Operating (per each data input) RESET = VDD, VI = VIH(AC) or VIL(AC), CLK & CLK switching 50% duty cycle RESET = VDD, VI = VIH(AC) or VIL(AC), CLK & CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle IOH = -20mA IOL = 20mA IO = 20mA, TA = 25oC VI = VREF + 310 mV VICR=1.25V, VI(PP) = 360mV VI = VDD or GND VDDQ 2.3V 2.3V -2.7V VDDQ 0.2 2.3V 1.95 2.3V -2.7V 2.3V 2.7V 2.7V 52 0.2 0.35 +5 10 A A mA MIN TYP MAX -1.2 UNITS V 75 IO = 0 2.5V / z 15 / clock MHZ/ data 20 20 4 rOH rOL rO(D) Output High Output Low [rOH - rOL] each separate bit Data Inputs CLK and CLK RESET 2.3V-2.7V 2.3V-2.7V 2.5V 7 7 13.5 13 2.5 2.5V 2.5 2.5 3.5 3.5 3.5 pF Ci Silego Technology Inc. (408) 327-8800 5 PRELIMINARY Data is subject to change. May 28, 2003 SLGSSTVF16859H/V SLGSSTVF16859V DC Electrical Characteristics - ( For PC3200) TA = 0 - 70oC; VDD = 2.6 +/-0.1V, VDDQ = 2.6 +/-0.1V; (unless otherwise stated) SMBL VIK VOH VOL II IDD All Inputs PARAMETERS CONDITIONS II = -18mA IOH = -100A IOH = -8mA IOL = 100A IOL = 8mA VI = VDD or GND Standby (Static) RESET = GND Operating (Static) VI = VIH(AC) or VIL(AC), RESET = VDD Dynamic operating (clock only) IDDD Dynamic Operating (per each data input) RESET = VDD, VI = VIH(AC) or VIL(AC), CLK & CLK switching 50% duty cycle RESET = VDD, VI = VIH(AC) or VIL(AC), CLK & CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle IOH = -20mA IOL = 20mA IO = 20mA, TA = 25oC VI = VREF + 310 mV VICR=1.25V, VI(PP) = 360mV VI = VDD or GND VDDQ 2.5V 2.5V -2.7V VDDQ 0.2 2.5V 1.95 2.5V -2.7V 2.5V 2.7V 2.7V 52 0.2 0.35 +5 10 A A mA MIN TYP MAX UNITS -1.2 V 75 IO = 0 2.6V / z 15 / clock MHZ/ data 20 20 4 rOH rOL rO(D) Output High Output Low [rOH - rOL] each separate bit Data Inputs CLK and CLK RESET 2.5V-2.7V 2.5V-2.7V 2.6V 7 7 13.5 13 2.5 2.5V 2.5 2.5 3.5 3.5 3.5 pF Ci Silego Technology Inc. (408) 327-8800 6 PRELIMINARY Data is subject to change. May 28, 2003 SLGSSTVF16859H/V Timing Requirements1: (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PARAMETERS VDD = 2.5V + 0.2V MIN MAX fclock Clock frequency 210 tW 2.5 Pulse duration CLK,CLK high or low 5 tACT 22 Differential active time tINACT Differential inactive time6 tS tH Notes: Data before CLK Setup time, slow slew rate3 & 4 Data after CLK Hold time, slow slew rate3 & 4 Hold time, fast slew rate2 & 4 Setup time, fast slew rate2 & 4 22 0.65 0.75 0.65 0.8 UNITS MHz ns ns ns ns ns ns ns , CLK , CLK 1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate of > 1V/ns. 3 - For data signal input slew rate of > 0.5V/ns and < 1V/ns. 4 - CLK, CLK signals input slew rate of > 1V/ns. 5 - Data input must be held low for a minimum time (tACT max) after RESET driven high 6 - Data and CLK,CLK inputs must be held at valid logic (high or low) levels for a minimum time (tINACT max) after RESET driven low Switching Characteristics:( For PC1600/2100/2700) (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL From To VDD = 2.5V + 0.2V (Input) (Output) MIN TYP MAX fmax tPD tPHL CLK, CLK RESET Q Q Q tPDSS1 CLK, CLK 210 1.1 1.1 2.6 2.9 5 UNITS MHz ns ns ns Switching Characteristics:( For PC3200) (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL From To VDD = 2.6V + 0.1V (Input) (Output) MIN TYP MAX fmax tPD tPDSS tPHL 1 UNITS MHz 210 CLK, CLK CLK, CLK RESET Q Q Q 1.1 1.1 2.2 2.48 5 ns ns ns Silego Technology Inc. (408) 327-8800 7 PRELIMINARY Data is subject to change. May 28, 2003 SLGSSTVF16859H/V From output under test CL = Test Point 30pF(1) . . RL = 500 Load Circuit RESET LVCMOS input tINACT IDD(2) VDD VDD/2 VDD/2 0V tACT Timing Input tPLH VICR VICR tPHL VI(PP) 90% 10% IDDH IDDL Output VDDQ/2 VOH VDDQ/2 VOL Voltage and Current Waveforms Inputs Active and Inactive Times Voltage Waveforms - Propagation Delay Times tw Input VIH VREF VREF VIL RESET LVCMOS input VIH VDD/2 VIL tPHL Output VOH VDDQ/2 VOL Voltage Waveforms - Pulse Duration Voltage Waveforms - Propagation Delay Times Timing Input VICR VI(PP) tS Input VREF tH VIH VREF VIL Voltage Waveforms - Setup and Hold Times Notes: 1. CL includes measurement probe and jig capacitance. 2. Conditions for IDD testing are with clock and data inputs at VDD or GND, and IO = 0mA 3. All input pulses are supplied by generators having: Zo=50, input slew rate = 1 V/ns + 20% ( unless otherwise specified). 4. The outputs are measured individually with one transition per measurement. 5. VIH = VREF + 310mV (AC levels) for differential inputs. VIH = VDDQ for LVCMOS input. 6. VIL = VREF - 310mV (AC levels) for differential inputs. VIL = GND for LVCMOS input. 7. tPLH = tPHL = tPD Silego Technology Inc. (408) 327-8800 8 PRELIMINARY Data is subject to change. May 28, 2003 SLGSSTVF16859H/V Package dimensions: SLGSSTVF16859H 64-TSSOP (56-pin drawing shown for reference) Silego Technology Inc. (408) 327-8800 9 PRELIMINARY Data is subject to change. May 28, 2003 SLGSSTVF16859H/V Package dimensions: SLGSSTVF16859V 52-VFQFN Silego Technology Inc. (408) 327-8800 10 PRELIMINARY Data is subject to change. May 28, 2003 SLGSSTVF16859H/V Ordering Information: Package type TSSOP-64pin 6.1mm body VFQFN VLLD-2 56pin 8.0x8.0mm body VFQFN VLLD-2 56pin 8.0x8.0mm body Package suffix H V V Topside marking SLGSSTVF16859H SLGSSTVF16859V SLGSSTVF16859V Ordering code SLGSSTVF16859H-TR (2,000 pcs/Reel) SLGSSTVF16859V-TR (2,000 pcs/Reel) SLGSSTVF16859V (2,000 pcs/Tray) Silego Technology Inc. reserves the right at any time to change specifications and circuitry without notice. Silego Technology Inc. does not assume responsibility for use of circuitry described. Circuit patent licenses are not implied. Silego Technology Inc. products are not authorized for use as critical components in life support devices or systems without obtaining express written approval from the president of Silego Technology Inc. A component is a critical component if failure to perform affects safety, effectiveness, or causes failure of the life support system. These systems are intended for surgical implant into the body, or support or sustain life, or whose failure to perform when properly used can be reasonably expected to result in injury to the user. Silego Technology Inc. (408) 327-8800 11 PRELIMINARY Data is subject to change. May 28, 2003 |
Price & Availability of SLGSSTVF16859V-TR
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |